A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
نویسندگان
چکیده
منابع مشابه
A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
In a modern three-dimensional integrated circuit (3D IC), vertically stacked dies are interconnected using through silicon vias. 3D ICs are subject to undesirable temperature-cycling phenomena such as through silicon via protrusion as well as void formation and growth. These cycling effects that occur during early life result in opens, resistive opens, and stress induced carrier mobility reduct...
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TSV-based 3D-SICs significantly impact core-based systemon-chip (SOC) design. Testing of core-based dies in 3D-SICs introduces new challenges [1], [2]. In order to test the dies in a stack, the embedded cores, and the TSVs, a test access mechanism (TAM) must be included on the die to transport test data to the cores, and a 3D TAM is needed to transfer test data to the die from the stack input/o...
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3D Stacked IC fabrication, using Through-SiliconVias, is a promising technology for future integrated circuits. However, large temperature gradients may exacerbate early-lifefailures to the extent that the commercialization of 3D Stacked ICs is challenged. The effective detection of these early-lifefailures requires that burn-in is performed when the IC’s temperatures comply with the thermal ma...
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ژورنال
عنوان ژورنال: Journal of Electronic Testing
سال: 2015
ISSN: 0923-8174,1573-0727
DOI: 10.1007/s10836-015-5541-5